For the synchronous transmission of digital data for typical systems, a transmitting unit transmits a data signal at a constant rate as determined by a clock local to the transmitting unit, and a receiving unit attempts to receive the data signal at the same constant rate. The transmitting unit may transmit the data signal without a clock signal as the system then requires less than one-half of the bandwidth necessary for the transmission of a data signal with a clock signal. To receive transmitted data signals with minimized errors, then, the receiving unit attempts to recover the clock signal associated with the data signal.
To recover the clock signal, the receiving unit may use a phase-locked loop (PLL) clock recovery system that includes a phase detector and a voltage controlled oscillator (VCO) that controls the frequency of the clock local to the receiving unit. The phase detector detects the phase difference between the received data signal and the clock local to the receiving unit (i.e., phase error), and then modulates the frequency of this local clock to bring the local clock into approximately the same phase and frequency as the received data signal. Thus, PLL circuits are used to maintain the local clock in a specific phase relationship with the received data signal. PLL circuits are used in a wide variety of applications including frequency synthesizers, analog modulators, digital modulators, analog demodulators, digital demodulators, and clock recovery
One prior PLL circuit consists of a phase detector that produces an output voltage proportional to the phase difference of the two input signals. The prior PLL circuit also comprises a voltage-controlled-oscillator that produces an ac output signal whose frequency is proportional to the input control voltage. Because the phase detector of the prior PLL circuit produces an output voltage proportional to the phase difference, the PLL circuit utilized linear control of the voltage-controlled-oscillator. However, because of the linear control of the voltage-controlled-oscillator, the prior PLL circuit had a peaking transfer function and exhibited peaking in the passband. The peaking in turn limits the PLL's noise filtering characteristics.
Another prior PLL circuit consists of a phase detector that produces an output voltage independent of the magnitude of the phase difference of the two input signals. The phase detector either produces a high voltage potential which accelerates the clock signal coming out of the voltage-controlled-oscillator or produces a low voltage potential which delays the clock signal coming out of the voltage-controlled-oscillator. As such, the phase detector produces a digital signal to control the voltage-control-oscillator. Because the output voltage of the phase detector is not proportional to the phase difference, this technique is characterized as nonlinear control of the voltage-controlled-oscillator. The nonlinear characteristic of the PLL circuit gives it a non-peaking transfer function and eliminates peaking in the passband. However, the PLL circuit has relatively poor run-length tolerance and introduces jitter (noise) into the system.
Thus, what is needed is a PLL circuit with a non-peaking transfer function, enhanced run-length tolerance and improved jitter performance.